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Physical Design Engineer

MediaTek

This is a Full-time position in Austin, TX posted July 4, 2021.

Responsible for high performance block implementation (RTL to GDSII).

Perform block level floorplanning, pin placement and power grid implementation.Implement block level placement, CTS and routing.

Close the design to meet timing, power budget and area.

Run physical verification flows (DRC/LVS/EM/IR), implement fixes to meet the requirements.

Implement ECO’s to address functional bugs, timing and physical verification violations.

Responsible for generation and maintenance of block level STA constraints.

Run STA regression and publish timing status.

Responsible for timing model generation and support successful integration of blocks into SOC.

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