RISC DV Lead / RISC DV engineers

Date: 19-Feb-2022
Location: Austin, Texas
Company: LTTS

• Lead a microprocessor verification team

• Create verification plans for RISC-V CPU designs

• Utilize coverage-driven constrained-random verification methodologies such as UVM to execute verification plans

• Collaborate with design engineers in debugging and finding solutions to simulation failures

• Make significant individual contributions while also providing guidance to team members

• Participate with other VLSI teams in continually improving verification methodologies

• Participate in industry standards organizations
About you:

• Demonstrated expertise in coverage-driven constrained-random verification.

• Experience in HDL languages such as Verilog, VHDL, or SystemVerilog

• Experience with software programming languages such as C / C++
Your experience includes:

• Demonstrated expertise in coverage-driven constrained-random verification using methodologies such as UVM

• Experience in HDL languages such as Verilog, VHDL, or SystemVerilog

• Experience with software programming languages such as C / C++

• 10+ years of experience in digital verification

• Bachelor’s Degree in Electrical Engineering, Computer Engineering or Computer Software and 10+ years’ experience.** A post-graduate degree is preferred or equivalent education and experience