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RTL Design Engineer- Interconnect


This is a Full-time position in Austin, TX posted April 7, 2021.

As a Memory System / Interconnect Design Engineer, you will be part of the Systems and Software team focused on next-generation interconnects targeting high-end mobile, networking, and enterprise markets. You will contribute to the specification, microarchitecture and RTL design of high-performance, energy-efficient interconnects. This opportunity is specific to a confidential project, and as part of this small and talented team, you will be able to expand your technical breadth relating to leading-edge interconnects, including multi-chip, IO acceleration, and new memory technologies. In addition, your close collaboration with other Austin-based CPU and System IP engineering teams leads to complete IP solutions to address the performance, power and cost requirements for almost all application markets.

What will I be accountable for?

As an RTL Design Engineer, you would be accountable for one or more functional blocks of the Interconnect while working closely with performance modeling, validation, and implementation teams to meet all functional requirements and performance, power, area (PPA) goals. Typical accountabilities include:

  • Understanding the high-level specification and requirements of one or more functional blocks of the Interconnect
  • Define the Micro-architecture for the blocks
  • Develop Verilog RTL logic design for the blocks
  • Collaborate with verification team on the test plan development for the blocks and verification closure
  • Debug functional or performance issues with the RTL using simulation and debug tools
  • Analyze synthesis/timing reports, identify and address critical areas to meet the PPA targets


Job Requirements:What skills, experience and qualifications do I need?

  • Education BS or MS in Electrical Engineering or Computer Engineering
  • Prior RTL design experience is required.
  • An ideal candidate will have at least 2+(10+) and maybe even more than 4+(15+) years of work experience in microprocessor, SoC, memory controller and interconnect IP design.

Technical Attributes

  • Experience with interconnect and bus architectures (with proficiency in IO acceleration, PCIe, system caching, QoS)
  • CPU or compute subsystem memory micro-architecture.
  • Knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI) is a plus.
  • Experience with Verilog or VHDL, coupled with design synthesis targeted to achieve specified frequency, power, and area targets
  • Processor system knowledge including basic understanding of SoC systems as well as operating system software

Personal Attributes

  • Demonstrate enthusiasm, drive and diligence
  • Work well in a team environment
  • Have excellent written and verbal communication skills
  • Be motivated to continuously develop skills and accept a variety of responsibilities as part of contributing to the design center’s success
  • Be able to travel for training or occasional customer interaction

What are the desired behaviors for this role?

At Arm, we are guided by our core beliefs that reflect our rare culture and guide our decisions, defining how we work together to defy ordinary and shape extraordinary:

We Not I

  • Take daily responsibility to make the Global Arm community thrive
  • No individual owns the right answer. Brilliance is collective
  • Information is crucial, share it
  • Realize that we win when we collaborate — and that everyone misses out when we don’t

Passion for Progress

  • Our differences are our strength. Widen and mix up your network of connections
  • Difficult things can take unexpected directions. Stick with it
  • Make feedback positive and expansive, not negative and narrow
  • The essence of progress is that it can’t stop. Grow with it and own your own progress

?Be Your Brilliant Self

  • Be quirky not egocentric
  • Recognize the power in saying ‘I don’t know’
  • Make trust our default position
  • Hold strong opinions lightly
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